The invention relates generally to biasing a region in a semiconductor integrated circuit to a selected voltage level and, more particularly, to a system for preventing undesired charge injection for bipolar latchup in a CMOS integrated circuit.
Recent advances in CMOS technology have allowed memory circuit designers to realize the power reduction inherent in CMOS design while achieving high density. However, as memory cell size decreases to allow for high density arrays, the susceptibility of alpha particle induced soft errors in the array increases. A CMOS DRAM utilizing PMOS memory cells disposed in an N-well formed in P substrate significantly reduces this soft error susceptibility.
The N-well must be biased to a higher voltage level than the PMOS transfer gates in the memory cells and the P channel bit line connections to reverse bias the semiconductor junctions formed between these PMOS elements and the N-well. If these junctions are forward biased, then undesired charge injection takes place between the PMOS memory cells and the bit line connections in the N-well, thereby destroying the information stored in the memory. Additionally, the various P type and N type regions in a CMOS array form bipolar transistors. If the above-described junctions are forward biased then the transistors may form a feedback current loop to allow high substrate current. This phenomenon is termed bipolar latch up.
The active cycle of the memory is initiated by clocking a control signal received at a control input of the memory. During the active cycle, selected word lines are clocked to couple selected storage cells to the bit lines. The voltage level on half the bit lines in the array are pulled to the power supply level, V.sub.CC, by the sense amps.
The N-well may be biased to a multiple of V.sub.CC, e.g., 1.5 V.sub.CC, to prevent forward biasing during the active cycle. A CMOS memory having an N-well biased at 1.5 V.sub.CC is described in an article by Shimohigashi, et al. entitled "An N-Well CMOS Dynamic RAM," IEEE Journal of Solid State Circuits, Vol. SC-17, No. 2, April, 1982, pp. 344-348.
However, during initial power-up, or during an excursion in the value of the power supply voltage (V.sub.CC bump), the bit line voltage may exceed the N-well bias voltage and forward bias the semiconductor junction. The large capacitance of the N-well causes the rate of change of the N-well bias voltage level to be slower than the rate of change of the bit line voltage level. Thus, the bit line voltage may exceed the N-well voltage for a short time. During this time the above-described problems of charge injection and bipolar latchup will be present if the memory is in the active cycle.
Accordingly, a system for preventing the forward biasing of the junctions between the bit lines and the N-well during the active cycle of the memory is greatly needed in the industry. This system must protect the memory during initial power-up and during a V.sub.CC bump. Additionally, the system must consume low power so as not to degrade the low power dissipation inherent in CMOS technology.